A non-volatile semiconductor memory device represented by EEPROM has a structure in which a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode are stacked on a semiconductor substrate. Information is written by applying a high voltage to the control electrode and implanting electrons into the charge storage layer from the semiconductor substrate via the tunnel insulating film.
In addition, a structure using a conductive charge storage layer represented by a polycrystalline silicon for the aforementioned charge storage layer is generally called a floating gate type. Further, a structure using an insulating charge storage layer represented by a silicon nitride film is generally called a floating trap type.
An element isolation insulating layer whose main constituent is SiO2 is formed on side faces of the stacked structure formed of a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode. Surrounding the charge storage layer with the element isolation insulating layer suppresses discharge of charge from the charge storage layer.
When a defect exists in an interface between the upper insulating layer and the element isolation insulating layer, this defect degrades reliability of the semiconductor memory device, which is regarded as a problem. Causes of this problem include damage due to a reactive ion etching process or an ion implanting process, and dangling bond formation due to a difference in film type between the upper insulating layer and the element isolation insulating layer.
As a measure for damage during the reactive ion etching process and the ion implanting process, a structure in which a spacer is formed on a side face of a control electrode of a floating trap type memory is proposed.
However, in the aforementioned structure, voltage is not applied to a lower part of the spacer, and there occurs an area where charges are not implanted in an end portion of the charge storage layer. Accordingly, there is a concern that diffusion of stored charges to an end portion of the charge storage layer during retention causes variation in threshold of the semiconductor memory device.